View 74LVC74ABQ_5008579.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet product speci?cation supersedes data of 2002 jun 18 2003 may 26 integrated circuits 74lvc74a dual d-type flip-flop with set and reset; positive-edge trigger
2003 may 26 2 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a features 5 v tolerant inputs for interfacing with 5 v logic wide supply voltage range from 1.2 to 3.6 v cmos low power consumption direct interface with ttl levels inputs accept voltages up to 5.5 v complies with jedec standard no. 8-1a esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v specified from - 40 to +85 c and - 40 to +125 c. description the 74lvc74a is a high-performance, low-voltage, si-gate cmos device, superior to most advanced cmos compatible ttl families. the 74lvc74a is a dual positive edge triggered d-type flip-flop with individual data (d) inputs, clock (cp) inputs, set ( sd) and ( rd) inputs, and complementary q and q outputs. the set and reset are asynchronous active low inputs and operate independently of the clock input. information on the data input is transferred to the q output on the low-to-high transition of the clock pulse. the d inputs must be stable one set-up time prior to the low-to-high clock transition, for predictable operation. schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times. quick reference data gnd = 0 v; t amb =25 c; t r =t f 2.5 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. the condition is v i = gnd to v cc . symbol parameter conditions typical unit t phl /t plh propagation delay ncp to nq, n qc l = 50 pf; v cc = 3.3 v 2.5 ns n sd to nq, n qc l = 50 pf; v cc = 3.3 v 2.5 ns n rd to nq, n qc l = 50 pf; v cc = 3.3 v 2.5 ns f max maximum clock frequency c l = 50 pf; v cc = 3.3 v 250 mhz c i input capacitance 4.0 pf c pd power dissipation capacitance per gate v cc = 3.3 v; notes 1 and 2 15 pf
2003 may 26 3 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a function tables table 1 see note 1. table 2 see note 1. note to tables 1 and 2 1. h = high voltage level; a) l = low voltage level; b) x = dont care; c) - = low-to-high cp transition; d) q n+1 = state after the next low-to-high cp transition. ordering information input output n sd n rd ncp nd nq n q lhxxhl hlxxlh llxxhh input output n sd n rd ncp nd nq n+1 n q n+1 hh - llh hh - hhl type number temperature range package pins package material code 74lvc74ad - 40 to +125 c 14 so14 plastic sot108-1 74lvc74adb - 40 to +125 c 14 ssop14 plastic sot337-1 74lvc74apw - 40 to +125 c 14 tssop14 plastic sot402-1 74LVC74ABQ - 40 to +125 c 14 dhvqfn14 plastic sot762-1
2003 may 26 4 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a pinning pin symbol description 11 rd asynchronous reset-direct input (active low) 2 1d data input 3 1cp clock input (low-to-high, edge-triggered) 41 sd asynchronous set-direct input (active low) 5 1q true ?ip-?op output 61 q complement ?ip-?op output 7 gnd ground (0 v) 82 q complement ?ip-?op output 9 2q true ?ip-?op output 10 2 sd asynchronous set-direct input (active low) 11 2cp clock input (low-to-high, edge-triggered) 12 2d data input 13 2 rd asynchronous reset-direct input (active low) 14 v cc supply voltage fig.1 pin configuration so14 and (t)ssop14. handbook, halfpage mna417 74 1 2 3 4 5 6 7 8 14 13 12 11 10 9 1rd 1d 1cp 1sd 1q 1q gnd 2q 2q 2sd 2cp 2d 2rd v cc fig.2 pin configuration dhvqfn14. handbook, halfpage 114 1rd v cc 7 2 3 4 5 6 1d 1cp 1sd 1q 1q 13 12 11 10 9 2rd 2d 2cp 2sd 2q 8 gnd 2q gnd (1) top view mdb105 (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input.
2003 may 26 5 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a fig.3 logic diagram. mna418 handbook, halfpage rd ff sd 410 q 1q 2q 1q 2q 5 9 2 12 3 11 6 8 q 1sd cp 2cp 1cp 2d 1d d 2sd 113 1rd 2rd fig.4 iec logic symbol. handbook, halfpage mna419 6 3 2 c1 4 s 1d 1 r 5 8 11 12 c1 10 s 1d 13 r 9 fig.5 functional diagram. handbook, halfpage rd ff sd 4 q 1q 1q 5 2 3 6 q 1sd cp 1cp 1d d 1 1rd mna420 rd ff sd 10 q 2q 2q 9 12 11 8 q 2sd cp 2cp 2d d 13 2rd
2003 may 26 6 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a fig.6 logic diagram (one flip-flop). handbook, full pagewidth mna421 sd cp rd d c c q c c c c c c q c c
2003 may 26 7 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. for so14 packages: above 70 c the value of p tot derates linearly with 8 mw/k. a) for (t)ssop14 packages: above 60 c the value of p tot derates linearly with 5.5 mw/k. b) for dhvqfn14 packages: above 60 c the value of p tot derates linearly with 4.5 mw/k. symbol parameter conditions min. max. unit v cc supply voltage for maximum speed performance 2.7 3.6 v for low-voltage applications 1.2 3.6 v v i input voltage 0 5.5 v v o output voltage 0 v cc v t amb ambient temperature - 40 +125 c t r ,t f input rise and fall times v cc = 1.2 to 2.7 v 0 20 ns/v v cc = 2.7 to 3.6 v 0 10 ns/v symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +6.5 v i ik input diode current v i <0 -- 50 ma v i input voltage note 1 - 0.5 +6.5 v i ok output diode current v o >v cc or v o <0 - 50 ma v o output voltage note 1 - 0.5 v cc + 0.5 v i o output source or sink current v o =0tov cc - 50 ma i cc , i gnd v cc or gnd current - 100 ma t stg storage temperature - 65 +150 c p tot power dissipation per package t amb = - 40 to +125 c; note 2 - 500 mw
2003 may 26 8 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a dc characteristics at recommended operating conditions; voltages are referenced to gnd (groun d=0v). symbol parameter test conditions min. typ. (1) max. unit other v cc (v) t amb = - 40 to +85 c v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- 0v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il ; i o = - 100 m a 2.7 to 3.6 v cc - 0.2 -- v i o = - 12 ma 2.7 v cc - 0.5 -- v i o = - 18 ma 3.0 v cc - 0.6 -- v i o = - 24 ma 3.0 v cc - 0.8 -- v v ol low-level output voltage v i =v ih or v il ; i o = - 100 m a 2.7 to 3.6 -- 0.2 v i o = - 12 ma 2.7 -- 0.4 v i o = - 24 ma 3.0 -- 0.55 v i li input leakage current v i = 5.5 v or gnd 3.6 - 0.1 5 m a i cc quiescent supply current v i =v cc or gnd; i o =0 3.6 - 0.1 10 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6v; i o =0 2.7 to 3.6 - 5 500 m a
2003 may 26 9 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a note 1. all typical values are measured at t amb =25 c. t amb = - 40 to +125 c v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- 0v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il ; i o = - 100 m a 2.7 to 3.6 v cc - 0.3 -- v i o = - 12 ma 2.7 v cc - 0.65 -- v i o = - 18 ma 3.0 v cc - 0.75 -- v i o = - 24 ma 3.0 v cc - 1.0 -- v v ol low-level output voltage v i =v ih or v il ; i o = - 100 m a 2.7 to 3.6 -- 0.3 v i o = - 12 ma 2.7 -- 0.6 v i o = - 24 ma 3.0 -- 0.8 v i li input leakage current v i = 5.5 v or gnd 3.6 -- 20 m a i cc quiescent supply current v i =v cc or gnd; i o =0 3.6 -- 40 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6v; i o =0 2.7 to 3.6 -- 5000 m a symbol parameter test conditions min. typ. (1) max. unit other v cc (v)
2003 may 26 10 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a ac characteristics gnd = 0 v; t r =t f 2.5 ns. symbol parameter test conditions min. typ. (1) max. unit waveforms v cc (v) t amb = - 40 to +85 c t phl /t plh propagation delay ncp to nq, n q see figs 7 and 9 1.2 - 15 - ns 2.7 1.0 2.7 6.0 ns 3.0 to 3.6 1.0 2.5 (2) 5.2 ns propagation delay n sd to nq, n q see figs 8 and 9 1.2 - 15 - ns 2.7 1.0 3.2 6.4 ns 3.0 to 3.6 1.0 2.5 (2) 5.4 ns propagation delay n rd to nq, n q see figs 8 and 9 1.2 - 15 - ns 2.7 1.0 3.2 6.4 ns 3.0 to 3.6 1.0 2.5 (2) 5.4 ns t w clock pulse width high or low see figs 7 and 9 2.7 3.3 -- ns 3.0 to 3.6 3.3 1.3 - ns set or reset pulse width low see figs 8 and 9 2.7 3.3 -- ns 3.0 to 3.6 3.3 1.7 (2) - ns t rem removal time set or reset see figs 8 and 9 2.7 1.5 -- ns 3.0 to 3.6 1.0 - 3.0 (2) - ns t su set-up time nd to ncp see figs 7 and 9 2.7 2.2 -- ns 3.0 to 3.6 2.0 0.8 (2) - ns t h hold time nd to ncp see figs 7 and 9 2.7 1.0 -- ns 3.0 to 3.6 0.0 - 0.7 (2) - ns f max maximum clock pulse frequency see figs 7 and 9 2.7 83 -- mhz 3.0 to 3.6 150 250 (2) - mhz t sk(0) skew note 3 3.0 to 3.6 -- 1.0 ns
2003 may 26 11 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a notes 1. all typical values are measured at t amb =25 c. 2. typical values are measured at v cc = 3.3 v. 3. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. t amb = - 40 to +125 c t phl /t plh propagation delay ncp to nq, n q see figs 7 and 9 1.2 --- ns 2.7 1.0 - 7.5 ns 3.0 to 3.6 1.0 - 6.5 ns propagation delay n sd to nq, n q see figs 8 and 9 1.2 --- ns 2.7 1.0 - 8.0 ns 3.0 to 3.6 1.0 - 7.0 ns propagation delay n rd to nq, n q see figs 8 and 9 1.2 --- ns 2.7 1.0 - 8.0 ns 3.0 to 3.6 1.0 - 7.0 ns t w clock pulse width high or low see figs 7 and 9 2.7 4.5 -- ns 3.0 to 3.6 4.5 -- ns set or reset pulse width low see figs 8 and 9 2.7 4.5 -- ns 3.0 to 3.6 4.5 -- ns t rem removal time set or reset see figs 8 and 9 2.7 1.0 -- ns 3.0 to 3.6 1.0 -- ns t su set-up time nd to ncp see figs 7 and 9 2.7 2.2 -- ns 3.0 to 3.6 2.0 -- ns t h hold time nd to ncp see figs 7 and 9 2.7 1.0 -- ns 3.0 to 3.6 0.0 -- ns f max maximum clock pulse frequency see figs 7 and 9 2.7 66 -- mhz 3.0 to 3.6 120 -- mhz t sk(0) skew note 3 3.0 to 3.6 -- 1.5 ns symbol parameter test conditions min. typ. (1) max. unit waveforms v cc (v)
2003 may 26 12 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a ac waveforms handbook, full pagewidth mna422 t h t su t h t phl t phl t w t plh t plh t su 1/f max v m v m v m v m v i gnd v i gnd ncp input nd input v oh v ol nq output v oh v ol nq output fig.7 the clock input (ncp) to output (nq, n q) propagation delays, the clock pulse width, the nd to ncp set-up, the ncp to nd hold times and the maximum clock pulse frequency. v m = 1.5 v at v cc 3 2.7 v; v m = 0.5v cc at v cc < 2.7 v; v ol and v oh are typical output voltage drop that occur with the output load. the shaded areas indicate when the input is permitted to change for predictable output performance
2003 may 26 13 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a handbook, full pagewidth mna423 t rem t phl t phl t w t plh t plh v m v m v m t w v m v m v i gnd v i gnd nsd input v i gnd nrd input ncp input v oh v ol nq output v oh v ol nq output fig.8 the set (n sd) and reset (n rd) input to output (nq, n q) propagation delays, the set and reset pulse widths and the n rd to ncp removal time. v m = 1.5 v at v cc 3 2.7 v; v m = 0.5v cc at v cc < 2.7 v; v ol and v oh are typical output voltage drop that occur with the output load.
2003 may 26 14 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a handbook, full pagewidth open gnd 50 pf 2 v cc v cc v i v o mna368 d.u.t. c l r t r l 500 w r l 500 w pulse generator s1 fig.9 load circuitry for switching times. v cc v i t plh /t phl 1.2 v v cc open 2.7 v 2.7 v open 3.0 to 3.6 v 2.7 v open definitions for test circuits: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator.
2003 may 26 15 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a package outlines unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
2003 may 26 16 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 0.2 7.9 7.6 1.03 0.63 0.9 0.7 1.4 0.9 8 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot337-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 1 7 14 8 q a a 1 a 2 l p q detail x l (a ) 3 mo-150 pin 1 index 0 2.5 5 mm scale ssop14: plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 a max. 2
2003 may 26 17 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
2003 may 26 18 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.65 1.35 y 1 2.6 2.4 1.15 0.85 e 1 2 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot762-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot762-1 dhvqfn14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 26 13 9 8 7 1 14 x d e c b a 02-10-17 03-01-27 terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
2003 may 26 19 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 220 c (snpb process) or below 245 c (pb-free process) C for all the bga packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 235 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 may 26 20 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso, vssop not recommended (6) suitable
2003 may 26 21 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 may 26 22 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a notes
2003 may 26 23 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74lvc74a notes
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613508/04/pp 24 date of release: 2003 may 26 document order number: 9397 750 10534

▲Up To Search▲

Price & Availability of 74LVC74ABQ

	To Download 74LVC74ABQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .